Hardware Counters

This walks you through measuring what's actually happening inside your CPU: cache miss rates, branch mispredictions, IPC, memory bandwidth. You'll use perf stat to collect PMU events, PAPI for portable counter access across architectures, and perf annotate to see which source lines are thrashing your cache. It includes raw event codes for Intel and AMD when the generic aliases aren't enough, plus thresholds for what "good" looks like (under 1% branch misses, IPC above 2.0 on modern x86). Honestly most useful when you've already profiled the hot path and need to understand why it's slow at the microarchitecture level, not for general optimization.

skills.sh installs: 590
GitHub stars: 279
last updated: Aug 21, 2026

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Install

$ npx -y skills add mohitmishra786/low-level-dev-skills --skill hardware-counters --agent claude-code

Installs into .claude/skills of the current project.

Files

Hardware Performance Counters

Purpose

Guide agents through hardware performance counter analysis: collecting PMU events with perf stat -e, using the PAPI library for portable counter access, interpreting cache miss rates and branch misprediction ratios, computing IPC, and correlating events to source lines with perf annotate.

Triggers

"How do I measure cache miss rate with perf?"
"How do I count branch mispredictions?"
"How do I compute IPC (instructions per clock) with perf?"
"How do I use the PAPI library for hardware counters?"
"How do I see which source lines cause the most cache misses?"
"How do I measure memory bandwidth with performance counters?"

Workflow

1. perf stat — basic counter collection

# Basic hardware event summary
perf stat ./prog

# Output:
#  Performance counter stats for './prog':
#
#      1,234,567,890      instructions
#        456,789,012      cycles
#         12,345,678      cache-misses         #    1.23 % of all cache refs
#         23,456,789      branch-misses        #    2.34 % of all branches
#
#       0.456789012 seconds time elapsed

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