Make

GNU Make

Purpose

Guide agents through idiomatic Makefile patterns for C/C++ projects: phony targets, pattern rules, automatic dependency generation, and common build idioms.

Triggers

• "How do I write a Makefile for my C project?"
• "My Makefile rebuilds everything every time"
• "How do I add dependency tracking to Make?"
• "What does $@, $<, $^ mean?"
• "I'm getting 'make: Nothing to be done for all'"
• "How do I convert my shell compile script to a Makefile?"

Workflow

1. Minimal correct Makefile for C

CC      := gcc
CFLAGS  := -std=c11 -Wall -Wextra -g -O2
LDFLAGS :=
LDLIBS  :=

SRCS    := $(wildcard src/*.c)
OBJS    := $(SRCS:src/%.c=build/%.o)
TARGET  := build/prog

.PHONY: all clean

all: $(TARGET)

$(TARGET): $(OBJS)
	$(CC) $(LDFLAGS) -o $@ $^ $(LDLIBS)

build/%.o: src/%.c | build
	$(CC) $(CFLAGS) -c -o $@ $<

build:
	mkdir -p build

clean:
	rm -rf build

Automatic variables:

• $@ — target name
• $< — first prerequisite
• $^ — all prerequisites (deduplicated)
• $* — stem (the % part in a pattern rule)
• $(@D) — directory part of $@

2. Automatic dependency generation